The present invention relates to a semiconductor device and, particularly, to a complementary monolithic semiconductor device including a p type well and an n type well.
As is well known in the art, there are two conductivity types in semiconductor, i.e., p type and n type. Semiconductor elements involving the structure of these opposite conductivity types include complementary elements such as pnp and npn bipolar junction transistors (BJT) and p channel and n channel field effect transistors (FET).
CMOS devices comprising n channel MOS FETs and p channel MOS FETs have the features of low power dissipation and high integration density, and are particularly suitable for use in logic circuits. Npn BJTs have the advantages of fast operation and large output.
For making semiconductor integrated circuits capable of achieving various functions, it is often required to form various semiconductor elements on the same substrate. In such cases, semiconductor substrates including p type and n type regions of relatively low impurity concentration are often required. For example, a CMOS large scale integrated circuit (LSI) is fabricated by forming n channel MOS FETs in the p type well and p channel MOS FETs in the n type well. A BI-CMOS LSI generally includes further n type wells each of which includes an npn BJT, in addition to the CMOS structure.
In semiconductor integrated circuits, isolation between elements is needed. In MOS FETs, charge carriers flow from the source to the drain along the surface, and isolation in the semiconductor bulk is usually unnecessary. In case the channel is induced along the surface, there is a risk of creating a parasitic MOS FET, and therefore each MOS FET is often surrounded .[.y.]. .Iadd.by .Iaddend.a region of high impurity concentration serving as a channel stopper. LOCOS (local oxidation of silicon) technique, in which thick oxide films are formed selectively, is also employed in many cases.
In a CMOS integrated circuit, a p type well and n type well coexist. The contiguous disposition of a p type well including n channel MOS FETs and an n type well including p channel MOS FETs entails a pnpn four-layer structure, resulting possibly in the formation of a parasitic thyristor. Turning-on of this thyristor causes "latch-up", precluding the related MOS FETs from operating as expected. In order to prevent latch-up, the pnp and npn BJTs constituting the thyristor need to have low current amplification factors .beta.(pnp) and .beta.(npn). This requirement may be met by increasing the thickness and/or increasing the impurity concentration of the n region and p region which serve as base regions of these BJTs.
One countermeasure is to form a p type well in an n type substrate (the remaining n type region becomes an n type well) and form n channel MOS FETs and p channel MOS FETs in the p type well and the n type well, respectively, with a groove formed deeper than the p type well around the p type well (side wall portion of the pn junction). The groove surface may be covered with the insulator and filled with an appropriate filler material. In the surface of the p type well .[.n.sub.+ .]. .Iadd.n.sup.+ .Iaddend.type regions for a channel MOS FET are doped, and in the surface of the n type well p.sup.+ type regions for p channel MOS FET are doped. The current path between the p.sup.+ type and n.sup.+ type regions is lengthened by the groove. In order to increase the distance from the p.sup.+ type region via the n type well (substrate) to the p type well, the groove is made to have a width of 1 .mu.m and a depth of 5.5 .mu.m, for example. A shallow p type well allows the npn type BJT, which is made up of the .[.n.sub.+ .]. .Iadd.n.sup.+ .Iaddend.type region, p type well and n type well (substrate), to have a larger current amplification factor .beta.(npn), and therefore the p type well is also made deeper, e.g., 4 .mu.m or more. Reference is made to Proceedings of Meeting of the Japanese Society of Applied Physics, Mar. 1982, p 692. However, despite the above dimensional consideration, the current amplification factor (npn) of the npn BJT can be non-negligibly large, and also there is a risk of "punch-through" between the n.sup.+ type region and the n type well (substrate).
In the case of BI-CMOS including vertical npn BJTs and CMOS FETs, the n type well including an npn BJT has an n.sup.+ type sub-collector buried region at the bottom. An n type well for the npn BJT and n type and p type wells for the CMOS FETs are formed in the p.sup.- type substrate. When the n type and p type wells for the CMOS FETs are provided at the bottom with an .[.n.sub.+ .]. .Iadd.n.sup.+ .Iaddend.type and p type buried regions, a noise current flowing in the wells can be drawn rapidly (due to a reduced well resistance), and the current amplification factor of the parasitic BJT can be suppressed small due to the presence of the base region having a high impurity concentration. However, if the p type well and n type well are disposed contiguously, resulting in the formation of the lateral BJT structure, the effect of latch-up prevention is limited. In the npn BJT, the potential varies even in the semiconductor bulk. Insulation for the npn BJT is made by surrounding its periphery with a thick thermal oxidation film which reaches the substrate, with a p.sup.+ type region being pushed down by the oxidation front and located under the oxide film. An oxide isolation region may also be provided between the p type and n type wells for the CMOS FETs. (Reference is made to Japanese Patent Unexamined Publication No. 57-188862.)
However, it is unavoidable that the buried region is expanded by further diffusion during the heat process. Diffusion can occur not only in the vertical (depth) direction, but also in .[.he.]. .Iadd.the .Iaddend.lateral direction. In order to separate the buried sub-collector sufficiently from the buried region of the contiguous well after the heat process, the oxide isolation region must be as wide a as 6-7 .mu.m or more. Such a dimension of the isolation region makes a bar against the improvement in the packing density. Furthermore, when a p.sup.+ region is formed under the oxide adjacent to the n.sup.+ type sub-collector for the isolation of the BJT, the capacitance of the npn BJT becomes large due to the p.sup.+ n.sup.+ junction, hampering the enchancement of the operating speed.
A preferred form of isolation for a complementary .[.intergrated.]. .Iadd.integrated .Iaddend.circuit is the use of an SOS substrate with the provision .[.od.]. .Iadd.of .Iaddend.oxide isolation reaching the .[.saphire.]. .Iadd.sapphire .Iaddend.substrate. Even in this case, reduction in the well resistance is limited, and the problem of increased manufacturing cost will result.